Silicon wafer

ABSTRACT

A silicon wafer is capable of reducing the warpage of the wafer occurring during a device process and allowing the subsequent processes, which have been suffered from problems due to severe warping of the wafer, to be carried out without problems and its manufacturing method. A silicon wafer according to the present invention is a silicon wafer in which there is formed a multilayered film constituting a semiconductor device layer on one main surface thereof in a device process, which is warped in a bowl shape due to an isotropic film stress of the multilayered film, and which has a (111) plane orientation.

TECHNICAL FIELD

The present invention relates to a silicon wafer serving as a substratematerial for a semiconductor device and, more particularly, to a siliconwafer suitably used as a substrate material of a highly laminatedsemiconductor device such as a three-dimensional NAND flash memory(hereinafter, referred to as “3DNAND”) and a processing method therefor.

BACKGROUND ART

A 3DNAND is recently attracting attention. The 3DNAND is a NAND memoryformed by vertically stacking memory cell arrays and, by setting thenumber of layers (number of layers of a word line) to 64, a storagecapacity as very large as 512 Gbit (64 GB) per single die can beachieved. Further, not by increasing density in a planar direction as ina conventional planar type NAND memory, but by increasing density in aheight direction, it is possible to provide a high performance flashmemory which is excellent not only in capacity, but also in writingspeed and power saving.

In the manufacture of a semiconductor device, films of various materialssuch as an oxide film, a nitride film, and a metal film are laminated ona silicon wafer so as to form a device structure. These laminated filmshave different film stresses depending on a film property and formationprocess conditions, which may produce a warp in the silicon wafer.Particularly, the 3DNAND is formed by vertically stacking several tensor more of memory elements, so that, correspondingly the number oflaminated films increases geometrically, with the result that the filmstress enormously increases in proportion to the increase in the numberof the laminated films, and this significantly increases the warpage ofthe silicon wafer. A large warp of the silicon wafer during a deviceprocess causes troubles that prevent processing in the subsequentprocesses, such as film formation, processing and inspection from beingperformed properly.

Regarding the manufacture of a semiconductor device having three or morewiring layers, Patent Document 1, for example, describes a semiconductordevice manufacturing method capable of reducing the warpage of a siliconsubstrate to equal to or less than a predetermined value withoutdepending on the type of a fabrication apparatus to be used and withoutusing a special interlayer film forming process. In this manufacturingmethod, assuming that the thickness of a silicon substrate is T (μm),the diameter thereof is D (inch), and the number of wiring layers is n,a silicon substrate satisfying

T≥62.4×D×[1.6(n−1)+1.0]^(1/2) is used to manufacture a semiconductordevice.

Further, Patent Documents 2 and 3 describe a method of manufacturing anepitaxial silicon wafer having high flatness by forming an epitaxiallayer on the surface of a silicon wafer for epitaxial growth having abowl-shaped warp (having a concave at the center thereof).

BACKGROUND ART LITERATURE Patent Document

-   Patent Document 1: Japanese Patent Application Laid-Open No.    H09-266206-   Patent Document 2: Japanese Patent Application Laid-Open No.    2008-140856-   Patent Document 3: Japanese Patent Application Laid-Open No.    2010-034461

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

However, the semiconductor device manufacturing method described inPatent Document 1 assumes that the film stress of the wiring layer isnot varied, and the formation process dependency of the film stress isignored. Actually, the film stress varies dependent on the formationprocess conditions, so that the amount of warpage cannot be evaluatedonly from the number of wiring layers. Thus, it is difficult to applythis manufacturing method. Further, when the number of wiring layers isset to 500 in a 12-inch silicon wafer, it is enough, according to theabove formula, to satisfy the thickness T of the silicon wafer ≥777.1μm, which, however, is substantially equal to the standard thickness(775 μm) of the 12-inch wafer and, thus, it is clear that the effect ofsuppressing the warping cannot be expected.

Further, the technique described in Patent Documents 2 and 3 is a methodof forming an initial wafer which is warped beforehand for reducing thewarp of a wafer after epitaxial growth and is not a method of reducingthe warp of the wafer during a device process. That is, even if a waferis warped due to the formation of a semiconductor device layer on suchan epitaxial wafer, it is impossible for the epitaxial wafer itself toreduce the warp. Further, even if an epitaxial growth process isregarded as a part of a device process, it is not clear how to calculatethe warp amount of a shape to be formed based on the warp amount to bereduced. Furthermore, the technique described in Patent Documents 2 and3 can be applied only to a case where a wafer is warped in a bowl shapeand cannot be applied to a case where a wafer is warped in a saddleshape.

The specifications such as the thickness, shape and crystal orientationof a silicon wafer are specified in advance independent of the amount orshape of the warp. Thus, even when the warp occurs in the silicon waferduring a device process, it is impossible to cope with the warp of thewafer because of the absence of the criterion for specification changeof the silicon wafer.

The object of the present invention is therefore to provide a siliconwafer capable of reducing the warp of the wafer occurring during amanufacturing process of a semiconductor device such as a 3DNAND andallowing the subsequent processes, which could suffer from problems dueto a large warp of the wafer, to be carried out without problems, and aprocessing method therefor.

Means for Solving the Problem

To solve the above problems, a silicon wafer according to the presentinvention is a silicon wafer in which there is formed a multilayeredfilm constituting a semiconductor device layer on one main surfacethereof in a device process, which is warped in a bowl shape due to anisotropic film stress of the multilayered film, and which has a (111)plane orientation.

By using a (111) silicon wafer having small orientation dependency of awarp when a wafer is warped in a bowl shape in a device process, it ispossible to enhance an effect of reducing the bowl-shaped warp. Thus,there can be provided a silicon wafer allowing the subsequent processes,which could suffer from problems due to a large warp of the wafer, to becarried out smoothly.

The oxygen concentration of the silicon wafer according to the presentinvention is preferably 8.0×10¹⁷ atoms/cm³ or more (ASTM F-121, 1979).The Young's modulus of a silicon crystal is improved as the oxygenconcentration in a crystal increases, so that a warp reduction effectcan be enhanced.

In the present invention, the semiconductor device layer preferablyincludes a 3DNAND flash memory. As described above, in the 3DNAND flashmemory, the number of stacked memory cell arrays is very large, so thatthe problem of the wafer warp is conspicuous. That is, when the numberof layers increases along with advance of a device process, the waferwarp also increases, and the warp amount exceeds an allowable rangebefore stacking of the topmost layer, which may make it impossible toadvance the device process further. However, according to the presentinvention, countermeasures against warping are taken for a device stillin a wafer state, so that the problem of the warp can be solved, thusavoiding the situation where it is impossible to advance the deviceprocess further.

Further, a silicon wafer according to the present invention is a siliconwafer in which there is formed a multilayered film constituting asemiconductor device layer on one main surface thereof in a deviceprocess, which is warped in a saddle shape due to an anisotropic filmstress of the multilayered film, and which has a (110) plane orientationand a <111> notch orientation.

By using a silicon wafer in which the plane orientation having a largeorientation dependency of the warp is (110) and the notch direction is<111> when a wafer is warped in a saddle shape in a device process, itis possible to make a direction in which the warp of the wafer becomeslarge coincide with the direction of a crystal orientation in whichYoung's modulus is large, whereby an effect of reducing thesaddle-shaped warp can be enhanced. Thus, there can be provided asilicon wafer allowing the subsequent processes, which could suffer fromproblems due to a large warp of the wafer, to be carried out smoothly.

The oxygen concentration of the silicon wafer according to the presentinvention is preferably 6.0×10¹⁷ atoms/cm³ or more (ASTM F-121, 1979).The Young's modulus of a silicon crystal is improved as the oxygenconcentration in a crystal increases, so that a warp reduction effectcan be enhanced.

In the present invention, the semiconductor device layer preferablyincludes a 3DNAND flash memory. As described above, in the 3DNAND flashmemory, the number of stacked memory cell arrays is very large, so thatthe problem of the wafer warp is conspicuous. That is, when the numberof layers increases along with advance of a device process, the waferwarp also increases, and the warp amount exceeds an allowable rangebefore stacking of the topmost layer, which may make it impossible toadvance the device process further. However, according to the presentinvention, countermeasures against warping are taken for a device stillin a wafer state, so that the problem of the warp can be solved, thusavoiding the situation where it is impossible to advance the deviceprocess further.

A silicon wafer processing method according to the present inventionincludes: preparing a silicon wafer having a (111) plane orientation;and forming a multilayered film constituting a semiconductor devicelayer on one main surface of the silicon wafer, wherein a bowl-shapedwarp generated due to an isotropic film stress of the multilayered filmis suppressed. According to the present invention, it is possible tosuppress the wafer warpage due to the film stress in a device process.

Further, a silicon wafer processing method according to the presentinvention includes: preparing a silicon wafer having a (110) planeorientation and a <111> notch orientation; and forming a multilayeredfilm constituting a semiconductor device layer on one main surface ofthe silicon wafer, wherein the direction of a saddle-shaped warpgenerated due to an anisotropic film stress of the multilayered film ismade to coincide with the notch orientation to suppress thesaddle-shaped warp. According to the present invention, it is possibleto suppress the wafer warpage due to the film stress in a deviceprocess.

Effects of the Invention

According to the present invention, there can be provided a siliconwafer manufacturing method capable of reducing the warpage of the waferoccurring during a device process and allowing the subsequent processes,which could suffer from problems due to a large warp of the wafer, to becarried out without problems.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view illustrating the configuration of asilicon wafer according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view illustrating the configuration of asilicon wafer according to a second embodiment of the present invention.

FIG. 3 is a schematic view for explaining the type of warp generatedwhen a film stress is applied to a flat silicon wafer, in which (a)illustrates a bowl-shaped warp, and (b) illustrates a saddle-shapedwarp.

FIG. 4 is a schematic view for explaining a difference in how the waferis warped due to a film stress applied to the silicon wafer.

FIG. 5 is a schematic perspective view illustrating an example of a filmformation pattern that applies an anisotropic film stress to a siliconwafer.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, preferred embodiments of the present invention will bedescribed with reference to the accompanying drawings.

FIG. 1 is a schematic plan view illustrating the configuration of asilicon wafer according to a first embodiment of the present invention.

As illustrated in FIG. 1, a silicon wafer 1A is a silicon wafer for ahighly laminated semiconductor device in which there is formed amultilayered film constituting a semiconductor device layer, such as a3DNAND flash memory, on one main surface thereof in a device process andwhich is warped in a bowl shape due to an isotropic film stress of themultilayered film. The plane orientation of the silicon wafer 1A is(111), and the notch orientation thereof is <110> or <112>. That is, anotch 2 is formed in a <110> or <112> direction.

The oxygen concentration of the silicon wafer 1A is preferably 8.0×10¹⁷atoms/cm³ or more (ASTM F-121, 1979). The Young's modulus of a (111)silicon wafer has oxygen concentration dependency, and thus it ispossible to enhance warp reduction effect when the oxygen concentrationis 8.0×10¹⁷ atoms/cm³ or more.

FIG. 2 is a schematic plan view illustrating the configuration of asilicon wafer according to a second embodiment of the present invention.

As illustrated in FIG. 2, a silicon wafer 1B is a silicon wafer for ahighly integrated semiconductor device in which there is formed amultilayered film constituting a semiconductor device layer on one mainsurface thereof in a device process and which is warped in a saddleshape due to an anisotropic film stress of the multilayered film. Theplane orientation of the silicon wafer 1B is (110), and the notchorientation thereof is <111>. That is, a notch 2 is formed in a <111>direction.

The oxygen concentration of the silicon wafer 1B is preferably 6.0×10¹⁷atoms/cm³ or more (ASTM F-121, 1979). The Young's modulus of a (110)silicon wafer has oxygen concentration dependency, and thus it ispossible to enhance the warp reduction effect when the oxygenconcentration is 6.0×10¹⁷ atoms/cm³ or more.

FIG. 3 is a schematic view for explaining the type of warp generatedwhen a film stress is applied to a flat silicon wafer, in which (a)illustrates a bowl-shaped warp, and (b) illustrates a saddle-shapedwarp.

The silicon wafer can be warped in a bowl shape or a saddle shape. Whenan isotropic film stress is applied to a flat silicon wafer, abowl-shaped warp is generated as illustrated in FIG. 3(a); while when ananisotropic film stress is applied to a flat silicon wafer, asaddle-shaped warp is generated as illustrated in FIG. 3(b). The bowlshape refers to a shape in which the entire outer periphery of the waferis displaced upward or downward relative to the center portion of thewafer. The saddle shape refers to a shape in which both end portions ofthe wafer in one of the X- and Y-directions thereof are displaced upward(or downward) relative to the center portion of the wafer and both endportions in other one of the X- and Y-directions are displaced downward(or upward) relative to the center portion.

The bowl shape refers to a shape in which the entire outer periphery ofthe wafer is displaced upward or downward relative to the center portionof the wafer. The saddle shape refers to a shape in which both endportions of the wafer in one of the X- and Y-directions thereof aredisplaced upward (or downward) relative to the center portion of thewafer and both end portions in other one of the X- and Y-directions aredisplaced downward (or upward) relative to the center portion.

FIG. 4 is a schematic view for explaining a difference in how the waferis warped due to a film stress applied to the silicon wafer.

As illustrated in FIG. 4, when a laminated film such as a wiring layerconstituting a semiconductor device is formed on the surface of thesilicon wafer, a film stress is generated in the silicon wafer, wherebya bowl-shaped warp as illustrated in (a) or a saddle-shaped warp asillustrated in (b) is generated. When such a warp of the waferincreases, various problems arise in the subsequent processes.

The reason that the silicon wafer is warped into a saddle shape during adevice process is that the signs of the film stresses of the filmsformed on the silicon wafer differ from each other to generateanisotropy of the film stress. For example, as illustrated in FIG. 4,when, in addition to a wiring layer in which a compressive stress in theX-direction is dominant, a wiring layer having a tensile stress in theY-direction perpendicular to the X-direction is formed, the compressivestress in the X-direction is intensified, with the result that thesilicon wafer is warped in a saddle shape.

The Young's modulus of a silicon crystal varies depending on a crystalorientation, that is, it has orientation dependency. Specifically, theYoung's modulus of a silicon crystal is 130 MPa in a [100] direction,170 MPa in a [110] direction, and 189 MPa in a [111] direction. Thesmaller the Young's modulus is, the easier deformation occurs. When thewafer is warped in a saddle shape, coincidence between a direction inwhich the warp is maximum and the direction of a crystal orientation inwhich Young's modulus is small makes the wafer more apt to be warped toincrease the warp amount. Conversely, coincidence between the directionin which the warp is maximum and the direction of a crystal orientationin which Young's modulus is large makes the wafer less likely to bewarped to reduce the warp amount.

Thus, in the present embodiment, when the wafer is warped in a saddleshape in a device process, the silicon wafer 1B in which the planeorientation having a large orientation dependency of the warp is (110)and the notch direction is <111> is used (see FIG. 2). Normally, asemiconductor device is formed in accordance with the notch direction ina device process, so that by matching the direction of the wiring layerto the notch direction, it is possible to make a direction in which thewarp of the wafer becomes large coincide with the direction of a crystalorientation in which Young's modulus is large, whereby an effect ofreducing the saddle-shaped warp can be enhanced.

Further, when the wafer is warped in a bowl shape in a device process,the silicon wafer 1A in which the plane orientation having noorientation dependency of the warp is (111) is used (see FIG. 1). Bymaking the Young's modulus of the silicon wafer isotropic in conformityto the isotropic film stress to be applied in a device process, aneffect of reducing the bowl-shaped warp can be enhanced.

While the present invention has been described based on the preferredembodiment, the present invention is not limited to the aboveembodiment, and various modifications may be made within the scope ofthe present invention. Accordingly, all such modifications are includedin the present invention.

For example, although the silicon wafer manufacturing method suitablefor manufacture of a 3DNAND has been described in the above embodiment,the present invention is not limited to this but may be applied tosilicon wafers for various semiconductor devices in which the wafer maybe warped due to the film stress.

EXAMPLES Example 1

Silicon wafer samples #1 to #16 having different plane orientations anddifferent notch orientations were prepared. Each of the wafer sampleswas grown by a CZ method and had a diameter of 300 mm and a thickness of775 μm. The plane orientations of the wafer samples were of three typesof (100), (110), and (111). The notch orientation of the wafer havingthe (100) plane orientation included two types of <110> and <100>. Thenotch orientation of the wafer having the (110) plane orientationincluded two types of <110> and <111>. The notch orientation of thewafer having the (111) plane orientation included two types of <110> and<112>. Variations in both the plane orientation and notch orientationamong the wafers used were within ±1°.

Then, the oxygen concentration of each wafer was measured. The oxygenconcentration was measured using a Fourier transform infraredspectroscopy (FT-IR) defined in ASTM F-121, 1979.

Then, a silicon oxide film having a thickness of 2 μm was formed on themain surfaces of the wafer samples #1 to #16 by a CVD process. As aresult, a convex bowl-shaped warp was generated. The measurement resultsconcerning the warp amounts (WARP) of the wafer samples are shown inTable 1.

TABLE 1 Oxygen concentration Wafer Wafer plane Notch (×10¹⁷ Warp amountsample orientation orientation atoms/cm³) (μm) #1 (100) <110> 8.5 612 #2(100) <110> 13.2 608 #3 (100) <100> 8.4 611 #4 (100) <100> 13.0 605 #5(110) <110> 7.2 789 #6 (110) <110> 12.9 762 #7 (110) <111> 8.2 785 #8(110) <111> 13.5 765 #9 (111) <110> 6.3 507 #10 (111) <110> 8.1 451 #11(111) <110> 10.6 443 #12 (111) <110> 12.5 441 #13 (111) <110> 13.8 448#14 (111) <112> 6.0 501 #15 (111) <112> 8.2 436 #16 (111) <112> 11.9 440

As is clear from Table 1, in the wafer samples #1 to #4 having the (100)plane orientation, a large warp of about 600 μm is generatedirrespective of the substrate oxygen concentration and notchorientation.

In the wafer samples #5 to #8 having the (110) plane orientation, alarge warp of about 770 μm is generated irrespective of the substrateoxygen concentration and notch orientation. Although the warp amount issmaller as the oxygen concentration becomes higher, there is found nosignificant difference.

In the wafer samples #9 to #16 having the (111) plane orientation, thewarp amount is reduced as compared to the wafers having the (100) and(110) plane orientations, irrespective of the notch orientation.Further, the wafer warp has oxygen concentration dependency, and thewarp reduction effect is particularly high when the oxygen concentrationis 8.0×10¹⁷ atoms/cm³ or more. This is presumably because increase inthe oxygen concentration improves the Young's modulus of a siliconcrystal.

The Young's modulus of a silicon crystal has orientation dependency inwhich it varies depending on the crystal orientation, so that when sucha film stress with little anisotropy as to cause a bowl-shaped warp isapplied, resistance to deformation is thought to be changed depending onthe plane orientation. From the above results, it can be said that it ispossible to suppress the warp to be a problem in a device process byusing the (111) wafer.

Example 2

As in Example 1, silicon wafer samples #17 to #31 having different planeorientations and different notch orientations were prepared, and theoxygen concentrations thereof were measured.

Then, a silicon oxide film having a thickness of 1 μm was formed on themain surfaces of the wafer samples #17 to #31 by a CVD process, followedby partial etching using a mask, and then a silicon nitride film havinga thickness of 0.7 μm was formed by a CVD process, followed by partialetching using a mask, whereby a film as illustrated in FIG. 5 wasproduced. For example, in a (100) wafer of sample #17, the silicon oxidefilm has a rectangular pattern elongated in a <110> direction, and thesilicon nitride film has a rectangular pattern elongated in a directionperpendicular to the longitudinal direction of the silicon oxide film.By the pattern obtained by synthesizing the silicon oxide and nitridepatterns, an anisotropic film stress is generated in the silicon wafer,causing a saddle-shaped warp. The measurement results concerning thewarp amounts (WARP) of the wafer samples are shown in Table 2.

TABLE 2 Oxygen concentration Wafer Wafer plane Notch (×10¹⁷ Warp amountsample orientation orientation atoms/cm³) (μm) #17 (100) <110> 5.7 478#18 (100) <110> 13.1 464 #19 (100) <100> 5.5 618 #20 (100) <100> 13.3621 #21 (110) <110> 5.7 553 #22 (110) <110> 7.8 559 #23 (110) <110> 12.9552 #24 (110) <111> 5.6 398 #25 (110) <111> 6.3 325 #26 (110) <111> 10.9318 #27 (110) <111> 12.9 312 #28 (111) <110> 5.4 513 #29 (111) <110>12.1 520 #30 (111) <112> 5.9 516 #31 (111) <112> 12.3 512

As is clear from Table 2, in the wafer samples #17 to #20 having the(100) plane orientation, the warp amount varies depending on thesubstrate oxygen concentration or notch orientation. Particularly, thewarp reduction effect is higher in the <110> notch than in the <100>notch. However, the <110> notch of the (100) wafer is the standardorientation of a wafer.

In the wafer samples #21 to #27 having the (110) plane orientation, thewarp amount varies depending on the substrate oxygen concentration ornotch orientation. Particularly, the warp reduction effect is high inthe <111> notch. Further, among the wafer samples #24 to #27 having the<111> notch, the samples #25, #26, and #27 having an oxygenconcentration of 6×10¹⁷ atoms/cm³ or more have a particularly high warpreduction effect.

In the wafer samples #28 to #31 having the (111) plane orientation, alarge warp of about 500 μm is generated irrespective of the substrateoxygen concentration and notch orientation. However, the <110> notch ofthe (111) wafer is the standard orientation of a wafer.

DESCRIPTION OF THE SYMBOLS

-   1A, 1B Silicon wafer-   2 notch

1. A silicon wafer in which there is formed a multilayered filmconstituting a semiconductor device layer on one main surface thereof ina device process, which is warped in a bowl shape due to an isotropicfilm stress of the multilayered film, and which has a (111) planeorientation.
 2. The silicon wafer as claimed in claim 1, wherein theoxygen concentration of the silicon wafer is 8.0×10¹⁷ atoms/cm³ or more(ASTM F-121, 1979).
 3. The silicon wafer as claimed in claim 1, whereinthe semiconductor device layer includes a 3DNAND flash memory.
 4. Asilicon wafer in which there is formed a multilayered film constitutinga semiconductor device layer on one main surface thereof in a deviceprocess, which is warped in a saddle shape due to an anisotropic filmstress of the multilayered film, and which has a (110) plane orientationand a <111> notch orientation.
 5. The silicon wafer as claimed in claim4, wherein the oxygen concentration of the silicon wafer is 6.0×10¹⁷atoms/cm³ or more (ASTM F-121, 1979).
 6. The silicon wafer as claimed inclaim 4, wherein the semiconductor device layer includes a 3DNAND flashmemory.